1. Field of the Invention
The present invention relates generally to designing integrated circuits ("ICs") and, more particularly, to the design of Application Specific Integrated Circuits ("ASICs").
2. Description of the Prior Art
ASICs are used extensively throughout digital computers and other types of electronic circuits. For example, ASIC System Logic Controller ("SLC") ICs perform various functions essential to a digital computer's operation including, in many instances, interfacing between a high-speed CPU bus and a slower speed Input/output ("I/O") bus. Similarly, an ASIC super I/O IC, which is coupled to a digital computer's slower speed I/O bus, provides one or more serial ports, one or more parallel ports, a floppy diskette drive controller, and an interface for an Integrated Drive Electronics ("IDE") hard disk drive. Via a Small Computer System Interface ("SCSI") bus, ASICs also interface between a digital computer system's bus and a peripheral device, such as a disk drive, a printer, a scanner, a tape drive, a CD ROM drive or an optical storage drive. Computer display controller cards; Video on Demand set-top boxes; communication network systems such as 10BaseT, 100BaseT and Gigabit Ethernet hubs, switches and routers; industrial embedded controllers such as those used in automobiles, process monitoring and control, portable and cellular telephones, games and household appliances; as well as special purpose systems used to access the Internet all use ASICs.
Because ASICs provide a truly cost-effective way of implementing a large number of digital logic circuits to perform a particular function, ASIC designers and IC fabricators have developed certain techniques for reducing the difficulty, expense and time required to design and debug an ASIC, and to manufacture the ASIC in quantity. One technique to facilitate implementing ASICs is known as a Gate Array. Using a Gate Array, an ASIC designer merely specifies interconnections among individual digital logic circuits arranged in a pre-specified two-dimensional array of logic gates. Alternatively, a designer may specify an ASIC by selecting Standard Cells from among a library of cells provided by an IC fabricator, specifying the location for Standard Cells on an IC chip, and specifying interconnections among the selected Standard Cells.
Because experience has established that ASICs are cost-effective, the number of circuits included in and the complexity of ASIC designs increases year by year. Obviously, increasing ASIC complexity increases the likelihood of design errors in engineering prototypes, and also increases the number of iterations required to obtain a design that is commercially practical.
Moreover, not only are ASIC designs becoming ever more complex, ASIC fabrication techniques are also advancing year by year. In the foreseeable future, ASIC geometry will decreases from 0.35 micron feature size to 0.25 micron, 0.18 micron or even smaller feature size, while the size of IC wafers used for ASIC fabrication will concurrently increase in diameter from 6 inches to 8 inches, and to 12 inches. More complex ASIC designs will also require increasing the number of metalization layers from the 2 or 3 layers used at present to 5 or more layers of metalization. Fabricating each layer of metalization requires a different IC mask. The compounding effects of using ever smaller feature size on ever larger diameter IC wafers with an increasing number of metalization layers will significantly increase the Non-Recurring Expense ("NRE") of ASIC design, debugging and development.
For example, in the future the price of masks used in ASIC fabrication will increase from $2,000 per mask at present for 0.8 micron feature size geometry on a 6 inch diameter wafer to $10,000 per mask for 0.35 micron feature size geometry on an 8 inch diameter wafer. Consequently, because an average of seventeen (17) to thirty (30) masks will, in general, be required to fabricate future ASICs, NRE for each engineering prototype run will increase from $50,000 to $90,000 at present to perhaps $250,000 in the foreseeable future. An anticipated increase in wafer diameter from 8 inches to 12 inches will further increase the NRE for fabricating engineering prototypes.
Compounding all of the preceding technological considerations, that will surely increase the NRE of ASIC engineering, is the business reality that product life cycles continue to decrease. Traditional 4 to 8 week turn-arounds for fabricating an ASIC engineering prototype combined with 12 to 14 week lead times for ASIC production are becoming too long for product life cycles. Ever decreasing product life cycles in comparison with an ASIC's production cycle makes ASIC inventory control more difficult. For example, a particular ASIC design may become obsolete before exhausting a conventional three month inventory of the ASIC product.
There exist alternative ICs which digital logic designers may, in some instances, substitute for an ASIC. These alternatives, some of which are known as Field Programmable Gate Arrays ("FPGAs"), Programmable Array Logic ("PALs"),or Gate Array Logic ("GALs"), permit a digital logic designer to electronically program an IC to perform an application specific digital logic function. Moreover, some of these devices are electronically re-programmable, which, obviously, dramatically shortens the time for, and expense of fabricating and debugging a prototype ASIC. Consequently, electronically creating an ASIC by merely programming a standard IC appears highly desirable in comparison with physically manufacturing an ASIC. Unfortunately, in many instances presently available programmable logic devices such as FPGAs, PALs and GALs prove excessively expensive, particularly for high-volume products. Moreover, such ICs cannot, in general, provide a circuit density and/or circuit performance comparable to those readily obtainable using ASICs, i.e. levels of circuit density and/or performance that are necessary to produce a state-of-the-art product.
To address the preceding difficulties in ASIC prototype fabrication, Laser Programmable Gate Arrays ("LPGA") have been developed which permits prototyping an ASIC in one day. However, LPGAs are suitable only for low volume ASIC production, while mass production requires conventional ASIC fabrication. Moreover, because a LPGA is a Gate Array, it cannot provide the circuit density of a conventional ASIC, nor can it achieve an ASIC's electrical performance. Moreover, laser ASIC prototyping appears to require complicated, expensive, high-precision prototyping equipment that must be located in a centralized facility to which designs are transmitted for prototype fabrication. Finally, it appears that it will be difficult for laser prototyping to effectively and fully exploit the small feature size that foreseeable ASICs will employ, or large number of devices which such ICs will provide. Thus, while ASIC prototype fabrication using LPGAs, in some instances, offers an improvement over conventional ASIC prototype fabrication, the NRE still remains costly in comparison with directly re-programmable FPGAS, PALs or GALS, and implementing an ASIC using a LPGA remains less convenient and more opaque to IC designers than directly programmable devices.
To obviate the preceding difficulties in ASIC design U.S. Pat. No. 5,687,325 discloses an application specific field programmable gate array ("ASFPGA") that includes at least two fixed functional units in a single IC chip. Depending upon a specific application for the ASFPGA, the fixed functional units may include one or more bus interfaces, event timers, an interrupt controller, a Direct Memory Access ("DMA") controller, system timers, a realtime clock, a Random Access Memory ("RAM"), a clock synthesizer, a RAM Digital-to-Analog Converter ("DAC"), a display interface, a register file, a compressed image encoder/decoder ("CODEC"), a micro-controller, or similar functional units. The ASFPGA also includes a general purpose field programmable gate array ("FPGA"). The FPGA is configurable to effect a specific digital logic circuit interconnection between fixed functional units. After the FPGA has been configured, the fixed functional units together with the FPGA perform all the functions specified for a particular ASIC design.
An alternative way of obviating the preceding difficulties, designers of ASICs have begun including pre-designed functional blocks in the ASICS. Presently functional blocks are available for ASIC design which include a Dynamic Random Access Memory ("DRAM") block, a Static Random Access Memory ("SRAM") block, an Electronically Erasable Programmable Read Only Memory ("EEPROM") block, a FLASH Memory block, a First-In/First-Out ("FIFO") block, a Reduced Instruction Set Computer ("RISC") microprocessor block, a Digital Signal Processor ("DSP") block, bus interface blocks such as an Industry Standard Architecture ("ISA") bus interface block, an Extended Industry Standard Architecture ("EISA") bus interface block, a Video Electronics Standards Association ("VESA") bus interface block, a Peripheral Component Interconnect ("PCI") bus interface block, a Universal Serial Bus (USB"), an Up/Down Frequency Converter block, a Frequency-Hopping Spread-Spectrum Modulator/Demodulator block, a Baseband Analog-to-Digital Converter ("ADC") and DAC block, a Serial Data I/O ("SIO") block, etc.
In developing an ASIC using functional blocks, designers seek to obtain data specifying a particular functional block in at least four (4) different ways. First, a functional block to be employed in a new ASIC design may be extracted from or re-used from a previous ASIC design. If a prior ASIC design lacks a particular functional block, the designer may sometimes obtain data specifying a needed functional block from the foundry which will fabricate the ASIC. If previously developed functional blocks or functional blocks available from a foundry are inadequate for a particular ASIC design, the designer may seek to license a functional block's design data from some third party who has already developed and tested it. Lastly, if data specifying a suitable functional block design cannot be obtained in any of the three (3) preceding ways, then the ASIC designer may develop a functional block specifically for the ASIC. As is readily apparent, once a functional block has been developed as a last resort for a particular ASIC design, that functional block then becomes available for reuse in a subsequent ASIC design.
While the use of functional blocks in ASIC design shortens the time required to develop and test a particular ASIC, the economies which compel the use of ASICs by system builders ultimately causes a commercial disadvantage for companies which purchase ASICs for assembly into systems. Because the functionality which systems assembled using ASICs is, to a significant extent, established by the functionality inherent in the ASICs' designs, competing companies which assemble systems using ASICs' experience difficulty in functionally differentiating among their respective competing products. That is, if the functionality inherent in the ASIC design controls or limits the functions that a system builder's product may provide, then systems from various different competing companies will then all possess and offer essentially the same functionality. If systems from various different competing companies all offer essentially the same function, the system builders can then compete primarily only on price and/or delivery. Consequently, system builders are always seeking ways in which they can functionally differentiate their products from those of their competitors even though the competing products are assembled using essentially identical ASICs.
One way in which system builders seek to functionally differentiate their products from those of their competitors is through functions provided by software included in the system. While the functionality provided by computer programs can be readily changed or enhanced to differentiate among competing systems, software can never provide system builders with complete freedom in differentiating among competing products because the performance provided by software functionality is generally several order of magnitude less than the performance which can be achieved if the functionality is embedded into an ASIC.
This performance difference between hardware and software also exemplifies the fact that in designing any digital computer system there always exist trade-offs between implementing a function in hardware or software. That is a system designer is always free to choose to implement a particular function in hardware, software, or a combination of hardware and software. While implementing a particular function in hardware almost inevitably results in better performance, implementing that function in hardware may require using a more expensive ASIC in the system which will ultimately result either in a higher price for the system, or reduced profit for the system builder. Thus, at present selecting particular ASICs to be assembled into a digital computer system essentially determines how system functionality is to be partitioned between hardware and software. Once ASICs have been chosen for a system, any functionality which the ASICs lack can be provided only by the system's software. That is, there presently does not exist any way system builders can enhance or add hardware functionality to an existing system design other than by redesigning the system to use different ASICs.